Senior Engineering ManagerNozomi Networks
Jan 2026 — June 2026
Leading the Arc and Arc Embedded projects — Nozomi's endpoint sensor line for industrial and IoT environments.
Industrial cybersecurity · Formal methods
Director of Engineering at Nozomi Networks · PhD in Formal Methods
I build and lead engineering teams that ship industrial cybersecurity software, and I have spent two decades applying formal methods — SAT, SMT, model checking — to hardware and safety-critical systems. I am the main architect of the OpenSMT solver, hold two US patents on applying formal verification to OT security, and have published extensively on constraint solving and verification.
2004 — present
July 2026 — Present
Leading Nozomi's on-prem wired sensor family line for industrial and IoT environments (N2OS, Arc, DevOs).
Jan 2026 — June 2026
Leading the Arc and Arc Embedded projects — Nozomi's endpoint sensor line for industrial and IoT environments.
Jan 2022 — Dec 2025
Managed engineering work across the Guardian and Remote Collector products, and led the Arc project from its early stages.
Jan 2019 — Dec 2021
Engineering team leader for the Guardian and Remote Collector projects.
Apr 2018 — Dec 2018
Development of SCADAGuardian, Nozomi's flagship OT network monitoring product.
Jun 2016 — Mar 2018
Sep 2014 — May 2016
Mar 2012 — Aug 2014
Aug 2011 — Feb 2012
Nov 2007 — Jul 2011
Jan 2007 — Mar 2007
Princeton, New Jersey. Development of decision procedures and their integration into the proprietary FSOFT suite.
Aug 2004 — Sep 2004
Development of scientific software in C/C++.
1999 — 2007
2004 — 2007
Formal methods based on constraint solving via SMT. 11 publications in international conferences or journals. Teaching assistant.
1999 — 2004
Final grade 110/110 cum laude — average exam grade 28.85/30.
L = cum laude. Grades out of 30.
2 granted · US
US 11,906,943 B2 · Granted Feb 2024
Extracts PLC programs from network traffic and translates ladder-diagram elements into an equivalent formal model, so security properties can be verified automatically.
US 11,831,671 B2 · Granted Nov 2023
Encodes network topology, known vulnerabilities and atomic attacks as a circuit-like formal model, then uses an SMT-based model checker whose counterexamples yield the attack paths.
SAT · SMT · Model checking
Paper
An SMT-based model checker with a rich API for creating, simulating and verifying state machines expressed as circuits, deployable as a container behind a REST API. Bit-precise safety verification, including integer and floating-point arithmetic, plus multi-property optimising engines for MC/DC test generation in avionics.
Talk
Slide deck accompanying the FMICS 2021 paper.